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december 2015 docid028308 rev 2 1 / 27 this is information on a product in full production. www.st.com tsb572 low - power, 2.5 mhz, rr io, 36 v bicmos operational amplifier datasheet - production data features low - power consumption: 380 a typ wide supply voltage: 4 v - 36 v rail - to - rail input and output gain bandwidth product: 2.5 mhz low input bias current: 30 na max no phas e reversal high tolerance to esd: 4 kv hbm extended temperature range: - 40 c to 125 c automotive grade small smd packages 40 v bicmos technology enhanced stability vs. capacitive load applications active filtering audio systems automotive power supplies industrial low/high side current sensing description the tsb572 dual operational amplifier off ers extended voltage operating range from 4 v to 36 v and rail - to - rail input/output. the tsb572 offers a very good speed/power consumption ratio with 2.5 mhz gain bandwidth product while consuming only 380 a typically at 36 v supply voltage. stability an d robustness of the tsb572 make it an ideal solution for a wide voltage range of applications. dfn8 3x 3 miniso8
contents tsb572 2 / 27 docid028308 rev 2 contents 1 package pin connections ................................ ................................ 3 2 absolute maximum ratings and operating conditions ................. 4 3 electrical characteristics ................................ ................................ 5 4 application information ................................ ................................ 17 4.1 operating voltages ................................ ................................ .......... 17 4.2 input pin voltage ranges ................................ ................................ .. 17 4.3 ra il - to - rail input ................................ ................................ ............... 17 4.4 input offset voltage drift over temperature ................................ ....... 18 4.5 long term input offset voltage drift ................................ .................. 18 4.6 capacitive load ................................ ................................ ................ 20 4.7 pcb layout recommendations ................................ ......................... 21 4.8 optimized application recommendation ................................ .......... 21 5 package information ................................ ................................ ..... 22 5.1 miniso8 package information ................................ ......................... 23 5.2 dfn8 3x3 package information ................................ ....................... 24 6 ordering information ................................ ................................ ..... 25 7 revision history ................................ ................................ ............ 26
tsb572 package pin connections docid028308 rev 2 3 / 27 1 package pin connections figure 1 : pin connections for each package (top view) 1. exposed pad can be left floating or connected to ground
absolute maximum ratings and operating conditions tsb572 4 / 27 docid028308 rev 2 2 absolute maximum ratings and operating conditions table 1: absolute maximum rat ings symbol parameter value unit v cc supply voltage (1) 40 v v id differential input voltage (2) 1 v in input voltage (3) (v cc - ) - 0.2 to (v cc + ) + 0.2 i in input current (4) 10 ma t stg storage temperature - 65 to 150 c t j maximum junction temperature 150 r thja thermal resistance junction to ambient (5) (6) miniso8 190 c/w dfn8 3x3 40 esd human body model (hbm) (7) 4 kv machine model (mm) (8) 100 v cdm: charged device model (9) 1.5 kv latc h - up immunity 200 ma notes: (1) all voltage values, except the differential voltage are with respect to network ground terminal. (2) differential voltages are the non - inverting input terminal with respect to the inverting input terminal. (3) v cc - v in must no t exceed 6 v, vin must not exceed 6 v. (4) input current must be limited by a resistor in - series with the inputs. (5) r th are typical values. (6) short - circuits can cause excessive heating and destructive dissipation. (7) according to jedec standard jesd22 - a11 4f. (8) according to jedec standard jesd22 - a115a. (9) according to ansi/esd stm5.3.1. table 2: operating conditions symbol parameter value unit v cc supply voltage 4 to 36 v v icm common mode input voltage range (v cc - ) - 0.1 to (v cc + ) + 0.1 t oper operati ng free - air temperature range - 40 to 125 c
tsb572 electrical characteristics docid028308 rev 2 5 / 27 3 electrical characteristics table 3: electrical characteristics at vcc = 4 v, vicm = vcc/2, tamb = 25 c, and rl connected to vcc/2 (unless otherwise specified) symbol parameter conditions min. typ. max. unit dc performance v io input offset voltage - 1.5 1.5 mv - 40 c < t < 125 c - 2.1 2.1 v io /t input offset voltage drift - 40 c < t < 125 c 1.5 6 v/c i io input off set current 2 15 na - 40 c < t < 125 c 35 i ib input bias current 8 30 - 40 c < t < 125 c 70 c in input capacitor 2 pf r in input impedance 1 t cmr common mode rejection ratio 20 log (v icm /v io ) v icm = (v cc - ) to (v cc+ ) - 1.5 v, v out = v cc /2 90 114 db - 40 c < t < 125 c 80 v icm = (v cc - ) to (v cc+ ), v out = v cc /2 75 97 - 40 c < t < 125 c 70 a vd large signal voltage gain r l = 10 k, v out = 0.5 to 3.5 v 90 100 - 40 c < t < 125 c 85 v oh high level output v oltage (drop voltage from (v cc+ )) r l = 10 k 19 60 mv - 40 c < t < 125 c 80 v ol low level output voltage r l = 10 k 12 50 - 40 c < t < 125 c 70 i out i sink v out = v cc 20 38 ma - 40 c < t < 125 c 5 i source v out = 0 v 10 32 - 40 c < t < 125 c 5 i cc supply current (per channel) no load, v out = v cc /2 340 430 a - 40 c < t < 125 c 500 ac performance gbp gain bandwidth product r l = 10 k, c l = 100 pf 1.5 2.2 mhz - 40 c < t < 125 c 1.2 ? m phase margin r l = 10 k, c l = 100 pf 45 degrees g m gain margin r l = 10 k, c l = 100 pf 5 db e
electrical characteristics tsb572 6 / 27 docid028308 rev 2 symbol parameter conditions min. typ. max. unit sr negative slew rate v in = 3.5 to 0.5 v, a v = 1, 10 % to 90 %, r l = 10 k, c l = 100 pf 0.50 0.78 v/s - 40 c < t < 125 c 0.37 positive slew rate v in = 0 .5 to 3.5 v, a v = 1, 10 % to 90 %, r l = 10 k, c l = 100 pf 0.50 0.89 - 40 c < t < 125 c 0.37 e n equivalent input noise voltage f = 1 khz 20 nv/hz f = 0.1 hz to 10 hz 0.7 vpp thd+n total harmonic distortion + noise f = 1 khz, v in = 3. 8 v pp , r l = 10 k, c l = 100 pf 0.001 %
tsb572 electrical characteristics docid028308 rev 2 7 / 27 table 4: electrical characteristics at vcc = 12 v, vicm = vcc/2, tamb = 25 c, and rl connected to vcc/2 (unless otherwise specified) symbol parameter conditions min. typ. max. unit dc performance v io input o ffset voltage - 1.5 1.5 mv - 40 c < t < 125 c - 2.1 2.1 v io /t input offset voltage drift - 40 c < t < 125 c 1.5 6 v/c i io input offset current 2 15 na - 40 c < t < 125 c 35 i ib input bias current 8 30 - 40 c < t < 125 c 70 c in input capacitor 2 pf r in input impedance 1 t cmr common mode rejection ratio 20 log (v icm /v io ) v icm = (v cc - ) to (v cc+ ) - 1.5 v, v out = v cc /2 100 123 db - 40 c < t < 125 c 90 v icm = (v cc - ) to (v cc+ ), v out = v cc /2 85 106 - 40 c < t < 125 c 80 svr supply voltage rejection ratio 20 log (v cc /v io ) v cc = 4 to 12 v 90 99 - 40 c < t < 125 c 80 a vd large signal voltage gain r l = 10 k, v out = 0.5 to 11.5 v 95 106 - 40 c < t < 125 c 90 v oh high level output v oltage (drop voltage from v cc+ ) r l = 10 k 38 100 mv - 40 c < t < 125 c 150 v ol low level output voltage r l = 10 k 16 70 - 40 c < t < 125 c 90 i out i sink v out = v cc 20 42 ma - 40 c < t < 125 c 8 i source v out = 0 v 15 35 - 40 c < t < 125 c 7 i cc supply current (per channel) no load, v out = v cc /2 360 450 a - 40 c < t < 125 c 530 ac performance gbp gain bandwidth product r l = 10 k, c l = 100 pf 1.6 2.4 mhz - 40 c < t < 125 c 1.3 ? m phase margin r l = 1 0 k, c l = 100 pf 50 degrees g m gain margin r l = 10 k, c l = 100 pf 6 db e
electrical characteristics tsb572 8 / 27 docid028308 rev 2 symbol parameter conditions min. typ. max. unit sr negative slew rate v in = 10.5 to 1.5 v, a v = 1, 10 % to 90 %, r l = 10 k, c l = 100 pf 0.53 0.82 v/s - 40 c < t < 125 c 0.40 positive slew rate v in = 1.5 to 10.5 v, a v = 1, 10 % to 90 %, r l = 10 k, c l = 100 pf 0.55 0.92 - 40 c < t < 125 c 0.40 e n equivalent input noise voltage f = 1 khz 20 nv/hz f = 0.1 hz to 10 hz 0.7 vpp thd+n total harmonic distortion + noise f = 1 khz, v in = 7 v pp , r l = 10 k, c l = 100 pf 0.0005 %
tsb572 electrical characteristics docid028308 rev 2 9 / 27 table 5: electrical characteristics at vcc = 36 v, vicm = vcc/2, tamb = 25 c, and rl connected to vcc/2 (unless otherwise specified) symbol parameter conditions min. typ. max. unit dc performance v io input offset v oltage - 1.5 1.5 mv - 40 c < t < 125 c - 2.1 2.1 v io /t input offset voltage drift - 40 c < t < 125 c 1.5 6 v/c v io long - term input offset voltage drift (1) t = 25 c 1.5 v/month i io input offset curren t 2 15 na - 40 c < t < 125 c 35 i ib input bias current 8 30 - 40 c < t < 125 c 70 c in input capacitor 2 pf r in input impedance 1 t cmr common mode rejection ratio 20 log (v icm /v io ) v icm = (v cc - ) to (v cc+ ) - 1.5 v, v out = v cc /2 105 129 db - 40 c < t < 125 c 95 v icm = (v cc - ) to (v cc+ ), v out = v cc /2 95 115 - 40 c < t < 125 c 90 svr supply voltage rejection ratio 20 log (v cc /v io ) v cc = 4 to 36 v 90 104 - 40 c < t < 125 c 85 a vd large signal voltag e gain r l = 10 k, v out = 0.5 to 35.5 v 95 114 - 40 c < t < 125 c 90 v oh high level output voltage (drop voltage from v cc+ ) r l = 10 k 78 150 mv - 40 c < t < 125 c 200 v ol low level output voltage r l = 10 k 30 90 - 40 c < t < 125 c 120 i out i sink v out = v cc 25 65 ma - 40 c < t < 125 c 10 i source v out = 0 v 20 50 - 40 c < t < 125 c 10 i cc supply current (per channel) no load, v out = v cc /2 380 470 a - 40 c < t < 125 c 550 ac performance gbp gain ban dwidth product r l = 10 k, c l = 100 pf 1.7 2.5 mhz - 40 c < t < 125 c 1.4 ? m phase margin r l = 10 k, c l = 100 pf 50 degrees g m gain margin r l = 10 k, c l = 100 pf 8 db e
electrical characteristics tsb572 10 / 27 docid028308 rev 2 symbol parameter conditions min. typ. max. unit sr negative slew rate v in = 22.5 to 13.5 v, a v = 1, 10 % to 90 %, r l = 10 k, c l = 100 pf 0.57 0.88 v/s - 40 c < t < 125 c 0.44 positive slew rate v in = 13.5 to 22.5 v, a v = 1, 10 % to 90 %, r l = 10 k, c l = 100 pf 0.60 1.00 - 40 c < t < 125 c 0.44 e n equivalent input noise voltage f = 1 khz 20 nv/hz f = 0.1 hz to 10 hz 0.7 vpp thd+n total harmonic distortion + noise f = 1 khz, v in = 7 v pp , r l = 10 k, c l = 100 pf 0.001 % notes: (1) typical value is based on the v io drift observed after 1000h at 125 c extrapolated to 25 c using arrhenius law and assuming an activation energy of 0.7 ev. the operational amplifier is aged in follower mode configuration (see section 4.5 ).
tsb572 electrical characteristics docid028308 rev 2 11 / 27 figure 2 : supply current vs. supply voltage figure 3 : input offset voltage distribution at vcc = 4 v figure 4 : input offset voltage distribution at vcc = 12 v figure 5 : input offset voltage distribution at vcc = 36 v figure 6 : input offset voltage vs. temperature at vcc = 36 v figure 7 : input offset voltage temperature variation distribution at vcc = 36 v
electrical characteristics tsb572 12 / 27 docid028308 rev 2 figure 8 : input offset voltag e vs. supply voltage figure 9 : input offset voltage vs. common - mode voltage at vcc = 4 v figure 10 : input offset voltage vs. common - mode voltage at vcc = 36 v figure 11 : inp ut bias current vs. temperature at vicm = vcc/2 figure 12 : input bias current vs. common - mode voltage at vcc = 36 v figure 13 : output current vs. output voltage at vcc = 4 v
tsb572 electrical characteristics docid028308 rev 2 13 / 27 figure 14 : output current vs. output voltage at vcc = 36 v figure 15 : output voltage (voh) vs. supply voltage figure 16 : output voltage (vol) vs. supply voltage figure 17 : negative slew rate at vcc = 36 v figure 18 : positive slew rate at vcc = 36 v figure 19 : slew rate vs. supply voltage
electrical characteristics tsb572 14 / 27 docid028308 rev 2 figure 20 : bode diagram at vcc = 4 v figure 21 : bode diagram at vcc = 36 v figure 22 : phase margin vs. output current at vcc = 4 v figure 23 : phase margin vs. output current at vcc = 36 v figure 24 : phase margin vs. capacitive load figure 25 : overshoot vs. capacitive load at vcc = 36 v
tsb572 electrical characteristics docid028308 rev 2 15 / 27 figure 26 : small step response vs. time at vcc = 4 v figure 27 : output desaturatio n vs. time figure 28 : amplifier behavior close to the rails at vcc = 36 v figure 29 : noise vs. frequency at vcc = 36 v figure 30 : noise vs. time at vcc = 36 v figure 31 : thd+n vs. frequency 1 0 1 0 0 1 0 0 0 10 0 0 0 0 2 0 4 0 6 0 8 0 1 0 0 @ v cc = 3 6v @ v cc = 1 2v @ v cc = 4 v e quivalen t inpu t n o ise v o l t age (n v / hz ) f r eq u e n c y ( h z ) v icm=vcc/2 t=25c
electrical characteristics tsb572 16 / 27 docid028308 rev 2 figure 32 : thd+n vs. output voltage figure 33 : psrr vs. frequency at vcc = 36 v figure 34 : channel separation vs. frequency a t vcc= 36 v
tsb572 application information docid028308 rev 2 17 / 27 4 application information 4.1 operating voltages the tsb572 can operate from 4 v to 36 v. the parameters are fully specified for 4 v, 12 v, and 36 v power supplies. however, the parameters are stable in the full v cc range. additionally, the main specifications are guaranteed in extended temperature ranges from - 40 to 125 c. 4.2 input pin voltage ranges the tsb572 has internal esd diode protection on the inputs. these diodes are connected between the inputs and each supply rail to protect the input transistors from el ectrical discharge. if the input pin voltage exceeds the power supply by 0.2 v, the esd diodes become conductive and excessive current can flow through them. without limitation this over current can damage the device. in this case, it is important to limit the current to 10 ma, by adding resistance on the input pin, as shown in figure 35: "input current limitation" . figure 35 : input current limitation 4.3 rail - to - rail input the tsb572 has rail - to - rail inputs. the input common mode range is extended from (v cc - ) - 0.1 v to (v cc+ ) + 0.1 v at t = 25 c. v in r 16 v v out + + - -
application information tsb572 18 / 27 docid028308 rev 2 4.4 input offset voltage drift over temperature the maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 c. the operational amplifier is one of the main circ uits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. the signal chain accuracy at 25 c can be compensated during production at application level. the maximum input voltage drift over temperatu re enables the system designer to anticipate the effect of temperature variations. the maximum input voltage drift over temperature is computed using equation 1 . equation 1 where t = - 40 c and 125 c. the tsb572 datash eet maximum value is guaranteed by measurements on a representative sample size ensuring a c pk (process capability index) greater than 1.3. 4.5 long term input offset voltage drift to evaluate product reliability, two types of stress acceleration are used: voltage acceleration, by changing the applied voltage temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by t he technology) with the ambient temperature. the voltage acceleration has been defined based on jedec results, and is defined using equation 2 . equation 2 where: a fv is the voltage acceleration factor is the voltage acceleration constant in 1/v, constant technology parameter ( = 1) v s is the stress voltage used for the accelerated test v u is the voltage used for the application the temperature acceleration is driven by the arrhenius model, and is defined in equation 3 . equation 3 where: a ft is the temperature acceleration factor e a is the activation energy of the technology based on the failure rate a f v e v s v u C . = ? v i o ? t ma x v i o t v i o 2 5 C t 2 5 c C = c a f t e e a k - - - - - - 1 t u 1 t s C = .
tsb572 application information docid028308 rev 2 19 / 27 k is the boltzmann constant (8.6173 x 10 - 5 ev.k - 1 ) t u is the temperature of the die when v u is used (k) t s is the temperature of the die under temperature stress (k) the final acceleration factor, a f , is the multiplication of the voltage acceleration factor and the temperature acceleration factor ( equation 4 ). equation 4 a f is calculated using the temperature and voltage defined in the mission profile of the product. the a f value can then be used in equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. equation 5 to evaluate the op amp reliability, a follower stress condition is used where v cc is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by jedec rules). t he v io drift (in v) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see equation 6 ). equation 6 the long term drift parameter (v io ), estimating the reliability per formance of the product, is obtained using the ratio of the v io (input offset voltage value) drift over the square root of the calculated number of months ( equation 7 ). equation 7 where v io drift is the measured drift v alue in the specified test conditions after 1000 h stress duration. v c c ma x v o p wi t h v i c m v c c 2 = = mont h s a f 1 0 00 h 1 2 mo n t h s 24 h 36 5 . 2 5 day s = / a f a f t a f v = ? v i o v i o dr i f t m o nth s =
application information tsb572 20 / 27 docid028308 rev 2 4.6 capacitive load driving large capacitive loads can cause stability problems. increasing the load capacitance produc es gain peaking in the frequency response, with overshoot and ringing in the step response. it is usually considered that with a gain peaking higher than 2.3 db an op amp might become unstable. generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads. figure 36: "stability criteria with a serial resistor at different supply voltages" shows the serial resistor that must be added to the output, to make a system st able. figure 37: "test configuration for riso" shows the test configuration using an isolation resistor, riso. figure 36 : stability criteria with a serial resistor at different supply voltages fi gure 37 : test configuration for riso c load v in + - v cc+ riso 10 k? v cc- v ou t
tsb572 application information docid028308 rev 2 21 / 27 4.7 pcb layout recommendations particular attention must be paid to the layout of the pcb tracks connected to the amplifier, load, and power supply. the power and ground traces are critical as they must provide adequate energy and grounding for all circuits. the best practice is to use short and wide pcb traces to minimize voltage drops and parasitic inductance. in addition, to minimizing parasitic impedance over the entire surface, a multi - via technique that connects the bottom and top layer ground planes together in many locations is o ften used. the copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance. 4.8 optimized application recommendation it is recommended to place a 22 nf capacitor as close as possible to the supply pin. a good decoupling will help to reduce electromagnetic interference impact.
package information tsb572 22 / 27 docid028308 rev 2 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are ava ilable at: www.st.com . ecopack ? is an st trademark.
tsb572 package information docid028308 rev 2 23 / 27 5.1 miniso8 package information figure 38 : miniso8 package outline table 6: minis o8 mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 1.1 0.043 a1 0 0.15 0 0.006 a2 0.75 0.85 0.95 0.030 0.033 0.037 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 d 2.80 3.00 3.20 0.11 0.118 0.126 e 4 .65 4.90 5.15 0.183 0.193 0.203 e1 2.80 3.00 3.10 0.11 0.118 0.122 e 0.65 0.026 l 0.40 0.60 0.80 0.016 0.024 0.031 l1 0.95 0.037 l2 0.25 0.010 k 0 8 0 8 ccc 0.10 0.004
package information tsb572 24 / 27 docid028308 rev 2 5.2 dfn8 3x3 package information figure 39 : dfn8 3x3 package outline and mechanical data
tsb572 ordering inf ormation docid028308 rev 2 25 / 27 6 ordering information table 7: order codes order code temperature range package packing marking TSB572IQ2T - 40 c to 125 c dfn8 3x3 tape and reel k31 tsb572iyq2t (1) k32 tsb572ist miniso8 k31 tsb572iyst (1) k32 notes: (1) automo tive qualification according to aec - q100.
revision history tsb572 26 / 27 docid028308 rev 2 7 revision history table 8: document revision history date version changes 12 - oct - 2015 1 initial release 17 - dec - 2015 2 section 2: "absolute maximum ratings and operating conditions" : updated esd, mm value. section 6: "ordering information" : removed footnote (1) from order code TSB572IQ2T.
tsb572 docid028308 rev 2 27 / 27 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or t o this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for applicati on assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is grante d by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st f or such product. st and the st logo are trademarks of st. all other product or service names are the property o f their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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